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Timer/counter structure
- Apr 19, 2018 -

The essence of the timer/counter is to add 1 counter (16 bits), which consists of two registers: high 8 bits and low 8 bits. TMOD is the Timer/Counter operating mode register, which determines the operating mode and function; TCON is the control register that controls the start and stop of T0 and T1 and sets the overflow flag.

Each pulse counter increments by one. When the counter is full (ie, FFFFH), a pulse is input to return the counter to zero. The overflow of the counter causes TF0 or TF1 to be set in TCON and an interrupt request is issued to the CPU ( Timer/Counter Interrupt Enable). If the timer/counter operates in the timed mode, it indicates that the timing has expired; if it operates in the counting mode, it indicates that the count value is full.


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